There is growing demand for memory devices having ever-greater capacity. A measure related to capacity is array efficiency; array efficiency is the ratio of actual memory circuitry (e.g., the area encompassing the wordlines and bitlines and storage elements) to the overall area of the memory device. A memory device having an 80% array efficiency, for example, would have 80% of its area covered by memory array circuitry as opposed to the peripheral supporting circuitry. High-capacity memory devices are sometimes broken down into a plurality of cross-point memory arrays or tiles. For highest capacity, these tiles are typically fabricated using very fine geometries. Each tile will typically require driver circuitry to control the voltages into the array of that tile. However, the driver logic for supporting tile operation reduces array efficiency. It is therefore preferable in many implementations to design a memory device with fewer large tiles instead of many small tiles, because fewer large tiles will require fewer instances of the supporting driver circuits and will, therefore, have greater array efficiency. However, with large tiles come other problems such as coupling between wordlines or bitlines within the array.